Clock generator

ABSTRACT

Systems and methods are disclosed to provide clock generation. In accordance with one embodiment, a clock generator chip is provided that is configurable and in-system programmable. The clock generator chip may provide programmable input circuits, programmable output circuits, and permit a JTAG boundary scan.

TECHNICAL FIELD

The present invention relates generally to electrical circuits and, moreparticularly, to clock generators.

BACKGROUND

Clock generator circuits are typically employed to generate one or moreclock output signals based upon a clock input signal. One drawback ofconventional clock generator circuits (e.g., clock generator integratedcircuits or chips) is their limited programmability.

For example, there is often limited programmability in terms ofinput/output signal types, input/output voltage levels, frequency range,and/or output banking structure. Furthermore, if programming isavailable, the programming may have to be performed by pin strapping,which is difficult to implement, inflexible, and may require theutilization of a number of pins.

Another drawback of conventional clock generator circuits is their lackof support for joint test action group (JTAG) or other automatedtesting. Consequently, it can often be cumbersome, time-consuming, andexpensive to test a circuit board having clock generator circuits andother components (e.g., microprocessors, field programmable gate arrays(FPGAs), or complex programmable logic devices (CPLDs)). As a result,there is a need for improved clock generation techniques.

SUMMARY

Systems and methods are disclosed herein to provide clock generation.For example, in accordance with an embodiment of the present invention,a clock generator chip is provided that is configurable and in-systemprogrammable to provide programmable input circuits, programmable outputcircuits, and permit a JTAG boundary scan. The clock generator chip maybe configurable by employing on-chip electrically erasable memory (e.g.,electrically erasable programmable read only memory (EEPROM)). Theprogrammable input circuits permit a wide variety of input voltagelevels, input signal types, and input frequency range. The programmableoutput circuits permit a wide variety of output voltage levels, outputsignal types, and output frequency. The clock generator chip may alsohave flexible output banking structures and a programmable outputimpedance.

More specifically, in accordance with one embodiment of the presentinvention, a clock generator includes a first circuit adapted to receivean input signal, having a possible range of voltage levels and signaltypes, and modify a frequency of the input signal by a firstprogrammable amount to generate a first input signal; a feedback loopcircuit adapted to receive a feedback signal and modify a frequency ofthe feedback signal by a second programmable amount to generate a secondinput signal; a phase-locked loop circuit adapted to receive the firstinput signal and the second input signal and provide a first outputsignal; and a second circuit adapted to receive the first output signaland modify a frequency of the first output signal to generate aplurality of second output signals having programmable frequencies,wherein the first and second programmable amount and the programmablefrequencies are determined by data stored in electrically erasablememory.

In accordance with another embodiment of the present invention, anintegrated circuit includes means for selecting from a plurality ofinput signals and generating a first input signal having a programmablefrequency; means for selecting from a plurality of feedback signals andgenerating a second input signal having a programmable frequency; aphase-locked loop adapted to receive the first input signal and thesecond input signal and generate a first output signal; means forreceiving the first output signal and generating second output signalshaving programmable frequencies; means for selecting from the secondoutput signals and providing output signals each having a programmablevoltage level, signal type, and output impedance; and means forproviding configurability and in-system programmability.

In accordance with another embodiment of the present invention, a methodof generating clock signals includes receiving an input signal, whereinthe input signal may be a single-ended signal type or a differentialsignal type; modifying a frequency of the input signal by an amountdetermined from data selected from memory to provide a first inputsignal; receiving a feedback signal; modifying a frequency of thefeedback signal by an amount determined from data selected from memoryto provide a second input signal; aligning a frequency and/or a phase ofthe first input signal and the second input signal to provide a firstoutput signal; modifying a frequency of the first output signal togenerate a plurality of second output signals having frequenciesdetermined from data selected from memory; and providing output signals,selected from the second output signals, which have programmable voltagelevels, signal types, and output impedances.

In accordance with another embodiment of the present invention, a clockgenerator includes an input circuit programmable to receive inputsignals of various signal types and voltage levels and to generate inresponse an input signal to a phase-locked loop (PLL); a phase-lockedloop adapted to receive the PLL input signal and to generate in responsea PLL output signal; and an output circuit adapted to receive the PLLoutput signal and be programmable to generate in response clock signalsof various signal types and voltage levels.

The scope of the invention is defined by the claims, which areincorporated into this section by reference. A more completeunderstanding of embodiments of the present invention will be affordedto those skilled in the art, as well as a realization of additionaladvantages thereof, by a consideration of the following detaileddescription of one or more embodiments. Reference will be made to theappended sheets of drawings that will first be described briefly.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block diagram illustrating a clock generator circuit inaccordance with an embodiment of the present invention.

FIG. 2 shows a block diagram illustrating a more detailed exemplaryimplementation of the clock generator circuit of FIG. 1 in accordancewith an embodiment of the present invention.

FIG. 3 shows a block diagram illustrating frequency selection for aclock generator circuit in accordance with an embodiment of the presentinvention.

FIG. 4 shows a block diagram illustrating frequency selections for aclock generator circuit in accordance with an embodiment of the presentinvention.

FIG. 5 shows a block diagram illustrating an exemplary output circuitfor a clock generator circuit in accordance with an embodiment of thepresent invention.

FIG. 6 shows a block diagram illustrating an exemplary output circuitfor a clock generator circuit in accordance with an embodiment of thepresent invention.

FIG. 7 shows a block diagram illustrating an exemplary output circuitwith output impedance control for a clock generator circuit inaccordance with an embodiment of the present invention.

FIG. 8 shows a block diagram illustrating an exemplary input circuit fora clock generator circuit in accordance with an embodiment,of thepresent invention.

FIG. 9 shows a block diagram illustrating an exemplary input circuit fora clock generator circuit in accordance with an embodiment of thepresent invention.

FIG. 10 shows a block diagram illustrating an exemplary input circuitfor a clock generator circuit in accordance with an embodiment of thepresent invention.

FIG. 11 shows a block diagram illustrating an exemplary input boundaryscan cell circuit for a clock generator circuit in accordance with anembodiment of the present invention.

FIG. 12 shows a block diagram illustrating an exemplary input boundaryscan cell circuit for a clock generator circuit in accordance with anembodiment of the present invention.

FIG. 13 shows a block diagram illustrating an exemplary input boundaryscan cell circuit for a clock generator circuit in accordance with anembodiment of the present invention.

FIG. 14 shows a block diagram illustrating an exemplary input boundaryscan cell circuit for a clock generator circuit in accordance with anembodiment of the present invention.

FIG. 15 shows a block diagram illustrating an exemplary output boundaryscan cell circuit for a clock generator circuit in accordance with anembodiment of the present invention.

The preferred embodiments of the present invention and their advantagesare best understood by referring to the detailed description thatfollows. It should be appreciated that like reference numerals are usedto identify like elements illustrated in one or more of the figures.

DETAILED DESCRIPTION

FIG. 1 shows a block diagram illustrating a clock generator circuit 100in accordance with an embodiment of the present invention. Clockgenerator circuit 100 may be formed as a separate integrated circuit(chip) or formed as part of a larger integrated circuit to provide clocksignals (internally or externally), while the larger chip also performsits other intended functions.

Clock generator circuit 100 includes an input clock divider (M) 102, afeedback loop divider (N) 104, a phase-locked loop (PLL) core 106,dividers 108, and in-system programmable (ISP) and JTAG circuits 110.Clock generator circuit 100 receives reference signals and externalfeedback signals via leads 112, control signals via leads 114, and JTAGor ISP input signals via leads 116. Clock generator circuit 100 providesoutput signals via leads 120 and JTAG and other signals via leads 118.

In general, clock divider 102 modifies a frequency of an input signal,such as a reference clock signal, by a programmable and selectableamount and provides the input signal to PLL core 106, while feedbackloop divider 104 divides an external or internal feedback signal by aprogrammable and selectable amount and provides the feedback signal toPLL core 106. PLL core 106 provides frequency and/or phase lock based onthe signals provided by clock divider 102 and feedback loop divider 104and generates an output signal, which is divided by a programmableamount by dividers 108 to provide selectable output signals via leads120. It should be understood that clock divider 102, feedback loopdivider 104, and divider 108 may be designed to multiply, divide, and/orleave unchanged a frequency of an input signal depending upon thedesired application.

Clock generator circuit 100 is in-system programmable and configurable(e.g., by electrically erasable memory) to provide a flexible clockgeneration system. For example, input signals received by leads 112 and114 may be of various signal types (e.g., LVCMOS, LVTTL, SSTL, HSTL,LVDS, and LVPECL) and voltage levels (e.g., 1.8V, 2.5V, and 3.3V). PLLcore 106 along with clock divider 102, feedback loop divider 104, anddividers 108 are also programmable and configurable to provide variousselectable clock frequencies. Output signals may also be of varioussignal types and voltage levels, as discussed similarly above for theinput signals, and also provide a programmable impedance control.Circuits 110 provide the ISP functionality and test functionality forclock generator circuit 100.

FIG. 2 shows a block diagram illustrating a clock generator circuit 200,which is a more detailed exemplary implementation for portions of clockgenerator circuit 100 of FIG. 1. Clock generator circuit 200 selects adesired reference input signal (REFIN) via input circuits 218 and amultiplexer 210 to provide to a clock divider 202, which programmablydivides its frequency and provides the reference input signal to a PLLcore 206 and to a multiplexer 216. Multiplexer 216 selects between clockdivider 202 (e.g., during system test or debug purposes) and PLL core206 to route their corresponding output signal to a divider 208.

A multiplexer 212 selects a desired feedback signal (FBIN), which isprovided to a multiplexer 214 that selects between the feedback signal(via input circuits 220) and an internal feedback signal and provides aselected signal to a feedback loop divider 204. Feedback loop divider204 programmably divides a frequency of the selected signal and providesit to PLL core 206.

PLL core 206 includes a phase frequency detector (PFD), a current chargepump and loop filter (ICP), and a voltage controlled oscillator (VCO).PLL core 206 may also have a programmable output frequency range byutilizing an internal voltage divider. A lock signal is provided whenPLL core 206 achieves frequency and phase lock.

Divider 208 divides a signal received from multiplexer 216 and providesclock signals having different frequencies that are selectable bymultiplexers 222 and driven out by output circuits 226. Skew control forthe output signals may be provided by skew circuits 224 and skew circuit228.

An output enable signal 232 is provided for each output circuit 226. Forexample, if output enable signal 232 is asserted, then the outputsignals from output circuit 226 are synchronously enabled. If outputenable signal 232 is deasserted, then the output signals from outputcircuit 226 are synchronously disabled.

In general, clock generator circuit 200 provides programmable features,such as programmable frequency range, programmable input/output signaltypes and voltage levels, and programmable output impedance. PLL core206 may be a fully integrated, high performance PLL core that can beconfigured as a zero delay buffer, a multiplier or a divider, and haveprogrammable output frequencies. For example, clock generator circuit200 may provide 20-buffered output signals from one master clock, witheach buffered output signal driving a terminated transmission line.

Clock divider 202, feedback loop divider 204, and divider 208 are eachprogrammable to allow very flexible output-to-input frequency ratios(e.g., 1 to 32). Furthermore, an external feedback path allows clockgenerator circuit 200 to achieve a zero delay between the referenceinput and the selected feedback output clock signal.

In this example (FIG. 2), output circuits 226 are arranged in ten banks,each with two possible output signal paths (e.g., one differentialsignal or two single-ended signals per bank). As shown, an additionalbank is included to provide an internal feedback path for feedback loopdivider 204. Each bank may have its own separate supply voltage (Vcco)and ground (Gndo) pins so that the output signals of the bank maysupport various output voltage levels (e.g., 1.8V, 2.5V, and 3.3V)independently of the other banks. Thus, for this example (ten banks, twooutput signal paths per bank), there are twenty possible output signals(if the banks are all configured as single-ended), which require tenseparate supply voltages and grounds.

Input circuits 218 and 220 and output circuits 226 may be configuredindependently to support single-ended or differential standards (e.g.,LVTTL, LVCMOS, HSTL, SSTL, LVPECL, and LVDS), which permits single-endedinput to single-ended output, single-ended input to differential output,differential input to single-ended output, and differential input todifferential output. Output circuits 226 may also have a programmableoutput impedance (e.g., to accommodate transmission-line impedance from40 to 70 ohms in 5 ohm increments). Thus, output circuits 226 may beable to drive transmission lines of 50 ohm impedance without requiringexternal on-board series resistors, which reduces parts andimplementation costs along with implementation time and effort. Outputcircuits 226 may also provide an independent clock invert function.

A profile select signal 230, as shown in FIG. 2, is provided to, forexample, control multiplexers 222 and also clock divider 202 andfeedback loop divider 204. Profile select signal 230 controlsmultiplexers 222 to perform frequency selection by, for example,selecting from up to four different sets of frequencies from divider208. Likewise, profile select signal 230 may also control clock divider202 and feedback loop divider 204 by selecting from one set of fourregisters to provide control signals for each. In addition, profileselect signal 230 may also control the skew settings by selecting oneset of four registers that define the various skew parameters.

For example, FIG. 3 shows a block diagram illustrating frequencyselection for clock generator circuit 200 in accordance with anembodiment of the present invention. Profile select signal 230 is routedto multiplexers 302, 306, and 310 corresponding to clock divider 202,feedback loop divider 204, and divider 208, respectively. A number ofregisters 304, 308, and 312 are associated with clock divider 202,feedback loop divider 204, and divider 208, respectively, to select adesired division ratio.

As an example, clock divider 202 and feedback loop divider 204 may eachhave division ratios from 1 to 32 and divider 208 may have divisionratios from 2, 4, 6, . . . , to 64. Profile select signal 203 (e.g., a2-bit signal) controls multiplexer 302 to select signals from one offour 5-bit registers 304, which determines the division ratio for clockdivider 202. Similarly, profile select signal 203 controls multiplexers306 and 310 to select signals from one of four 5-bit registers 308 and312, which determine the division ratio for feedback loop divider 204and divider 208, respectively. For example, registers 308 may store four5-bit values, selected from the range of 00000 to 11111, whichcorrespond to division ratios from 1 to 32, respectively.

Registers 304, 308, and 312 are each configurable to store 4 of 32possible settings for clock divider 202, feedback loop divider 204, anddivider 208. Thus, a user may configure registers 304, 308, and 312 withappropriate settings to produce desired clock frequencies, which areselectable via profile select signal 203. These settings stored byregisters 304, 308, and 312 may be changed by in-system programmingtechniques whenever a user desires. Registers 304, 308, and 312 may, forexample, be electrically erasable registers (e.g., formed by EEPROM).

These techniques may be applied a number of times, depending upon thenumber of selectable output clock frequencies desired. For example, iffive different output clock frequencies are desired, divider 208,multiplexer 310, and registers 312 may be repeated four more times (asshown in FIG. 4) to provide the five possibly different output clockfrequencies (freq-0 through freq-4). Thus, profile select signal 230(labeled FS pins) may function as a select signal for multiplexer 310for tapping 1 of 32 different tap points (frequency output points) ofdivider 208 to select each frequency.

By having a number of banks and a number of frequencies to select from,a flexible banking output structure may be provided. For example, if tenbanks and five frequencies are available, a user can select how to groupthe banks and the number of output signals of various frequencies basedupon a particular application. As an example, the ten banks may beconfigured to operate as one bank (e.g., same output voltage levels,signal types, and output impedance) at one frequency to provide 20output signals. As another example, the ten banks may be configured tooperate as two banks at one frequency or at two different frequencies toprovide 10 output signals from each bank. Thus, various combinations ofbanking output structure, voltage levels, signal types, frequencies,output impedance, etc. may be selected based upon techniques discussedherein in accordance with one or more embodiments of the presentinvention.

For this particular implementation having ten banks, there could be upto ten or twenty different frequencies depending upon whether the banksare configured as differential or single-ended, respectively. However,the number of different frequencies available for the banks may belimited. As shown in FIG. 2, profile select signal 230 controlsmultiplexers 222 to select from among the possible output clockfrequencies generated by divider 208. Consequently, the number ofdifferent frequencies available simultaneously is limited by the numberof dividers 208 (or number of different frequencies provided by divider208).

As discussed above for one exemplary implementation, the frequency rangeof operation for clock generator circuit 200 is determined by profileselect signal 230 and configuration bits stored by registers 304, 308,and 312. Thus, four different profiles may be selected for each bank byprofile select signal 230.

It should be understood that numerous modifications and variations arepossible with respect to one or more of the embodiments discussed inreference to FIG. 2. For example, rather than be limited by profileselect signal 230 having only two bits, one or more control signals maybe implemented to allow the independent selection of the entire range ofdivision or multiplication ratios for clock divider 202, feedback loopdivider 204, and divider 208, and also allow the selection from all ofthe possible frequencies from divider 208 for any of output circuits226. However, this would require a number of additional control signalpaths (e.g., external leads) along with possibly additional circuitry,board space, and implementation complexity. Thus, one or more of thesedisadvantages may be avoided and a user may be able to obtain desiredclock signals by utilizing one or more of the techniques discussedherein (e.g., as shown in FIGS. 3 and 4), including configurability andin-system programmability.

As shown in FIG. 2, input circuits 218 and 220 and output circuits 226are provided to programmably support a wide range of signal types andsignal levels. For example, the signal types may include un-terminatedsingle-ended interfaces (e.g., LVTTL and LVCMOS), terminatedsingle-ended interfaces (e.g., SSTL and HSTL, which require a voltagereference signal and possibly a termination voltage signal), anddifferential interface standards (e.g., LVDS and LVPECL). The signaltypes may also include DDR and QDR memory interface signals, such asdifferential HSTL or SSTL (e.g., to drive SDRAMs and SRAMs).

For example, FIGS. 5–7 show exemplary implementations for one of outputcircuits 226 (i.e., for one bank) for clock generator circuit 200 ofFIG. 2 in accordance with an embodiment of the present invention. FIG. 5illustrates an exemplary implementation employing a differential outputbuffer in conjunction with a pair of single-ended output buffers, whichmay be utilized to support various signal types. FIG. 6 shows amodification to the implementation of FIG. 5 to support differentialHSTL, SSTL, and LVDS with the same output buffer.

FIG. 7 shows a modification to the implementation of FIGS. 5 and 6 byincluding two separate differential output buffers (rather than the onedifferential output buffer of FIGS. 5 and 6). A variable resistance(labeled RS in FIGS. 5–7) represents a programmable output impedance ofthe single-ended output buffer, which may be matched to a line impedancefor series termination. The output impedance, for example, may have animpedance range from 40 to 70 ohms in 5 ohm steps.

Referring to FIG. 2, input circuits 218 and 220 may receive (for thisexemplary application) four pairs of differential or four single-endedinput signals. For example, when configured to receive a single-endedinput signal, input circuit 218 or input circuit 220 receives a signalon one input terminal, while the other input terminal is unused orreceives a reference voltage, depending upon the application orprogrammed input specification. FIG. 8 shows a block diagramillustrating an input circuit 800, which is an exemplary implementationfor one of four input circuits 218 or 220 shown in FIG. 2 in accordancewith an embodiment of the present invention. A VCM/VTT pin is provided,with VCM (common mode voltage) for differential signals and with VTT(termination voltage) for certain types of single-ended signals (e.g.,HSTL). A resistance (RT) is programmable, with for example a nominalcenter point of 50 ohm. As an example, FIGS. 9 and 10 illustrateexemplary applications for input circuit 800.

Clock generator circuit 100 (FIG. 1) and clock generator circuit 200(FIG. 2), in accordance with an embodiment of the present invention, maybe implemented to be compliant with JTAG testing, such as IEEE 1149.1standards (e.g., IEEE 1149.1-1993 standard). Additionally, clockgenerator circuits 100 and 200 may also be compliant with IEEE 1532standard describing configuration of programmable logic devices.

For JTAG support, FIG. 11 shows a block diagram illustrating anexemplary input boundary scan cell circuit 1100 for a clock generatorcircuit in accordance with an embodiment of the present invention.Circuit 1100 allows instructions to be performed, for example, asoutlined in the JTAG standard (IEEE 1149.1-1993, e.g., sample/preloadand EXTEST). Specifically, circuit 1100 in FIG. 11 illustrates exemplarycircuit operation during an EXTEST function (capture-DR).

FIG. 12 illustrates exemplary circuit operation for circuit 1100 duringsample/preload (for capture-DR (CDR), shift-DR (SDR), and update-DR(UDR)). Similarly, FIGS. 13 and 14 illustrate exemplary circuitoperation for circuit 1100 during EXTEST (for CDR, SDR, and UDR) andINTEST (for CDR, SDR, and UDR), respectively. Note that in FIGS. 11–14,shift/test paths are indicated by “S/T” and data flow is indicated by“D” while shaded multiplexers are considered do not care for thatparticular situation.

FIG. 15 shows a block diagram illustrating an exemplary output boundaryscan cell circuit 1500 for a clock generator circuit in accordance withan embodiment of the present invention. Circuit 1500, for example,supports full EXTEST and modes of operation, but does not support INTESTas the pins are output only.

In general, boundary scan cells (e.g., circuit 1100 and/or circuit 1500)are inserted appropriately on all input/output paths, clock paths, anddedicated input paths, except for voltage supply leads and fourdedicated 1149.1 TAP pins. The boundary scan cells provide IEEE 1149.1compliance and allow functional testing of the circuit board, on whichthe device (e.g., clock generator circuit 100) is mounted, through aserial scan path that can access all critical logic nodes. Internalregisters may be linked internally, which allows test data to be shiftedin and loaded directly onto test nodes, or test node data to be capturedand shifted out for verification. The device may also be linked into aboard-level serial scan path for more board-level testing.

As noted above, the device may also provide in-system programming (ISP)capability (e.g., IEEE 1532 compliant ISP). For example, the ISPcapability may be provided through the boundary scan test access port.The ISP capability provides a number of significant benefits, such asfor example rapid prototyping, lower inventory levels, higher quality,and the ability to make in-field modifications.

In accordance with one or more embodiments of the present invention, aconfigurable (e.g., via EEPROMs) and in-system programmable clockgenerator (e.g., circuit or chip) is provided. The clock generator mayprovide flexible programmable inputs that permit various input voltagelevels, input signal types, and input frequency range. The clockgenerator may provide flexible programmable outputs that permit variousoutput voltage levels, output signal types, and output frequency range.Furthermore, flexible output banking structures may be provided alongwith a programmable output impedance. The clock generator may alsopermit JTAG or other automated testing.

Embodiments described above illustrate but do not limit the invention.It should also be understood that numerous modifications and variationsare possible in accordance with the principles of the present invention.Accordingly, the scope of the invention is defined only by the followingclaims.

1. A clock generator comprising: a first circuit adapted to programmablyreceive an input signal, having a possible range of voltage levels andsignal types, and modify a frequency of the input signal by a firstprogrammable amount to generate a first input signal; a feedback loopcircuit adapted to receive a feedback signal and modify a frequency ofthe feedback signal by a second programmable amount to generate a secondinput signal, wherein the feedback signal is selected from an internalfeedback signal and an external feedback signal; a phase-locked loopcircuit adapted to receive the first input signal and the second inputsignal and provide a first output signal; and a second circuit adaptedto receive the first output signal and modify a frequency of the firstoutput signal to generate a plurality of second output signals havingprogrammable frequencies, wherein the first and second programmableamount and the programmable frequencies are determined by data stored inelectrically erasable memory.
 2. The clock generator of claim 1, furthercomprising input/output boundary scan circuits adapted to provide JTAGtest support for the clock generator.
 3. The clock generator of claim 2,wherein the JTAG test support provides IEEE 1149.1 compliance.
 4. Theclock generator of claim 1, wherein the clock generator is in-systemprogrammable.
 5. The clock generator of claim 4, wherein the clockgenerator is in-system programmable by supporting IEEE 1532 standards.6. The clock generator of claim 1, wherein the phase-locked loop circuitgenerates a lock signal when the first input signal and the second inputsignal are frequency and phase locked.
 7. The clock generator of claim1, wherein the first circuit comprises three buffers adapted toprogrammably accept single and differential signals.
 8. The clockgenerator of claim 1, wherein the signal types comprise single-endedsignals and differential signals.
 9. The clock generator of claim 1,further comprising a plurality of output circuits adapted to receive theplurality of second output signals and programmably provide a pluralityof third output signals having a range of selectable voltage levels,signal types, and output impedance.
 10. The clock generator of claim 9,wherein the output circuits are adapted to provide a flexible outputbanking structure.
 11. The clock generator of claim 1, furthercomprising a plurality of multiplexers that are controlled to selectfrom the electrically erasable memory, which determines the frequency ofthe first input signal, the second input signal, and the second outputsignals.
 12. An integrated circuit comprising: means for selecting froma plurality of input signals and generating a first input signal havinga programmable frequency; means for selecting from a plurality offeedback signals and generating a second input signal having aprogrammable frequency; a phase-locked loop adapted to receive the firstinput signal and the second input signal and generate a first outputsignal; means for receiving the first output signal and generatingsecond output signals having programmable frequencies; means forselecting from the second output signals and providing output signalseach having a programmable voltage level, signal type, and outputimpedance; and means for providing configurability and in-systemprogrammability.
 13. The integrated circuit of claim 12, furthercomprising means for testing the integrated circuit to provide IEEE1149.1 compliance.
 14. The integrated circuit of claim 12, furthercomprising means for selecting the programmable frequency for the firstinput signal and the second input signal and the programmablefrequencies for the second output signals.
 15. The integrated circuit ofclaim 12, wherein the signal type comprises single-ended signals anddifferential signals.
 16. A method of generating clock signals, themethod comprising: receiving an input signal, wherein the input signalmay be a single-ended signal type or a differential signal type;modifying a frequency of the input signal by an amount determined fromdata selected from memory to provide a first input signal; receiving afeedback signal selected from an internal feedback signal and anexternal feedback signal; modifying a frequency of the feedback signalby an amount determined from data selected from memory to provide asecond input signal; aligning a frequency and/or a phase of the firstinput signal and the second input signal to provide a first outputsignal; modifying a frequency of the first output signal to generate aplurality of second output signals having frequencies determined fromdata selected from memory; and providing output signals, selected fromthe second output signals, which have programmable voltage levels,signal types, and output impedances.
 17. The method of claim 16, furthercomprising providing configuration data to the memory.
 18. The method ofclaim 16, further comprising providing in-system programmability tomodify configuration data stored in the memory.
 19. The method of claim16, further comprising providing JTAG compliant functional testing. 20.A clock generator comprising: an input circuit programmable to receiveinput signals of various signal types and voltage levels and to generatein response an input signal to a phase-locked loop (PLL); a phase-lockedloop adapted to receive the PLL input signal and to generate in responsea PLL output signal; a clock divider circuit coupled between the inputcircuit and the phase-locked loop and programmable to modify a frequencyof the PLL input signal; and an output circuit adapted to receive thePLL output signal and be programmable to generate in response clocksignals of various signal types and voltage levels.
 21. The clockgenerator of claim 20, further including a clock divider circuit coupledbetween the phase-locked loop and the output circuit and programmable tomodify a frequency of the PLL output signal.
 22. The clock generator ofclaim 20, further including a feedback loop circuit programmable tomodify a frequency of a feedback signal and to provide the modifiedsignal as a second PLL input signal.
 23. The clock generator of claim20, further comprising input/output boundary scan circuits adapted toprovide JTAG test support.
 24. A method of generating a clock signal,the method comprising: programmably receiving input signals of varioussignal types and voltage levels and generating an input signal for aphase-locked loop (PLL); receiving the PLL input signal and generatingin response a PLL output signal; receiving the PLL output signal andprogrammably generating in response clock signals of various signaltypes and voltage levels; and providing JTAG support and IEEE 1532in-system programmable standards.
 25. The method of claim 24, furthercomprising programmably modifying a frequency of the PLL input signal.26. The method of claim 24, further comprising programmably modifying afrequency of the PLL output signal.
 27. The method of claim 24, furthercomprising programmably modifying a frequency of a feedback signal andproviding the modified signal as a second PLL input signal.